EFM32G-DK3550【PDF 445/467 页】KIT DEVELOPMENT EFM32 GECKO

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...the world's most energy friendly microcontrollers

29.5.20 LCD_FREEZE - Freeze Register

Offset

0x060

Reset

Access

Name

Bit Position

Bit

Name

Reset

Access

Description

31:1

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0

REGFREEZE

0

RW

Register Update Freeze

When set, the update of the LCD is postponed until this bit is cleared. Use this bit to update several registers simultaneously.

Value

0

1

Mode

UPDATE

FREEZE

Description

Each write access to an LCD register is updated into the Low Frequency domain as

soon as possible.

The LCD is not updated with the new written value.

29.5.21 LCD_SYNCBUSY - Synchronization Busy Register

Offset

0x064

Reset

Access

Name

Bit Position

Bit

Name

Reset

Access

Description

31:12

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

11

SEGD3H

0

R

LCD_SEGD3H Register Busy

Set when the value written to LCD_SEGD3H is being synchronized.

10

SEGD2H

0

R

LCD_SEGD2H Register Busy

Set when the value written to LCD_SEGD2H is being synchronized.

9

SEGD1H

0

R

LCD_SEGD1H Register Busy

Set when the value written to LCD_SEGD1H is being synchronized.

8

SEGD0H

0

R

LCD_SEGD0H Register Busy

Set when the value written to LCD_SEGD0H is being synchronized.

7

SEGD3L

0

R

LCD_SEGD3L Register Busy

Set when the value written to LCD_SEGD3L is being synchronized.

6

SEGD2L

0

R

LCD_SEGD2L Register Busy

Set when the value written to LCD_SEGD2L is being synchronized.

5

SEGD1L

0

R

LCD_SEGD1L Register Busy

Set when the value written to LCD_SEGD1L is being synchronized.

4

SEGD0L

0

R

LCD_SEGD0L Register Busy

Set when the value written to LCD_SEGD0L is being synchronized.

2011-04-12 - d0001_Rev1.10

445

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